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one technology way, p.o. box 9106, norwood. ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 functional block diagram r / w v dd1 ld control logic address decode 16 x 8 input registers rs v dd2 v ref v cc 16 x 8 dac registers 16 8-bit dac s cs en a3 a2 a1 a0 db7 db6 db5 db4 db3 db2 db1 db0 o0 o1 o2 o3 o4 o5 o6 o7 o8 o9 o10 o11 o12 o13 o14 o15 v ee d gnd1 d gnd2 dacgnd ad8600 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a 16-channel, 8-bit multiplying dac ad8600 features 16 independently addressable voltage outputs full-scale set by external reference 2 m s settling time double buffered 8-bit parallel input high speed data load rate data readback operates from single +5 v optional 6 v supply extends output range applications phased array ultrasound & sonar power level setting receiver gain setting automatic test equipment lcd clock level setting general description the ad8600 contains 16 independent voltage output digital-to- analog converters that share a common external reference input voltage. each dac has its own dac register and input register to allow double buffering. an 8-bit parallel data input, four ad- dress pins, a cs select, a ld , en , r/ w , and rs provide the digital interface. the ad8600 is constructed in a monolithic cbcmos process which optimizes use of cmos for logic and bipolar for speed and precision. the digital-to-analog converter design uses volt- age mode operation ideally suited to single supply operation. the internal dac voltage range is fixed at dacgnd to v ref . the voltage buffers provide an output voltage range that ap- proaches ground and extends to 1.0 v below v cc . changes in reference voltage values and digital inputs will settle within 1 lsb in 2 m s. data is preloaded into the input registers one at a time after the internal address decoder selects the input register. in the write mode (r/ w low) data is latched into the input register during the positive edge of the en pulse. pulses as short as 40 ns can be used to load the data. after changes have been submitted to the input registers, the dac registers are simultaneously up- dated by a common load en ld strobe. the new analog out- put voltages simultaneously appear on all 16 outputs. at system power up or during fault recovery the reset ( rs ) pin forces all dac registers into the zero state which places zero volts at all dac outputs. the ad8600 is offered in the plcc-44 package. the device is designed and tested for operation over the extended industrial temperature range of C40 c to +85 c. v dd1 dacgnd r/ w cs ?ddress rs v dd2 v ref v cc d gnd2 d gnd1 r-2r dac ld en v ee rs r/ w cs ?ddr en o x dac register input register db7...db0 figure 1. equivalent dac channel
ad8600Cspecifications single supply parameter symbol condition min typ max units static performance 1 resolution n 8 bits relative accuracy 2 inl C1 1/2 +1 lsb differential nonlinearity 2 dnl guaranteed monotonic C1 1/4 +1 lsb full-scale voltage v fs data = ff h 2.480 2.490 2.500 v full-scale tempco tcv fs data = ff h 20 ppm/ c zero scale error v zse data = 00 h , rs = 0, t a = +25 c +3.5 lsb v zse data = 00 h , rs = 0 +5 lsb reference input resistance r ref data = ab h 1.2 2 k w analog output output voltage range 2 ovr ss v ref = +2.5 v 0.000 2.500 v output current i out data = 80 h 2ma capacitive load c l no oscillation 50 pf logic inputs logic input low voltage v il 0.8 v logic input high voltage v ih 2.4 v logic input current i il 10 m a logic input capacitance 3 c il 10 pf logic outputs logic out high voltage v oh i oh = C0.4 ma 3.5 v logic out low voltage v ol i ol = 1.6 ma 0.4 v ac characteristics 3 slew rate sr for d v ref or fs code change 4 7 v/ m s voltage output settling time 2 t s1 1 lsb of final value, full-scale data change 2 m s voltage output settling time 2 t s2 1 lsb of final value, d v ref = 1 v, data = ff h 2 m s power supplies positive supply current i cc v ih = 5 v, v il = 0 v, no load 24 35 ma logic supply currents i dd1&2 v ih = 5 v, v il = 0 v, no load 0.1 ma power dissipation p diss v ih = 5 v, v il = 0 v, no load 120 175 mw power supply sensitivity pss d v cc = 5% 0.007 %/% logic power supply range v ddr 4.75 5.25 v positive power supply range 3 v ccr v dd 7.0 v notes 1 when v ref = 2.500 v, 1 lsb = 9.76 mv. 2 single supply operation does not include the final 2 lsbs near analog ground. if this performance is critical, use a negative supply (v ee ) pin of at least C0.7 v to C5.25 v. note that for the inl measurement zero-scale voltage is extrapolated using codes 7 10 to 80 10 . 3 guaranteed by design not subject to production test. specifications subject to change without notice. rev. 0 C2C (@ v dd1 = v dd2 = v cc = +5 v 5%, v ee = 0 v, v ref = +2.500 v, C40 c t a +85 c, unless otherwise noted)
parameter symbol condition min typ max units static performance 1 resolution n 8 bits total unadjusted error tue all other dacs loaded with data = 55 h C1 3/4 +1 lsb relative accuracy inl C1 1/2 +1 lsb differential nonlinearity dnl guaranteed monotonic C1 1/4 +1 lsb full-scale voltage v fs data = ff h , v ref = +3.5 v 3.473 3.486 3.500 v full-scale voltage error v fse data = ff h , v ref = +3.5 v C1 +1 lsb full-scale tempco tcv fs data = ff h , v ref = +3.5 v 20 ppm/ c zero scale error v zse data = 00 h , rs = 0, t a = +25 cC2 1+2 mv zero scale error v zse data = 00 h , all other dacs data = 00 h C1 +1 lsb zero scale error v zse data = 00 h , all other dacs data = 55 h 1/2 lsb zero scale tempco tcv zs data = 00 h , v cc = +5 v, v ee = C5 v 10 m v/ c reference input resistance r ref data = ab h 1.2 2 k w reference input capacitance 2 c ref data = ab h 240 pf analog output output voltage range ovr 1 v ref = +3.5 v 0.000 3.500 v output voltage range 2 ovr 2 v cc = v dd2 = +7 v, v ee = C0.7 v, v ref = 5 v 0.000 5.000 v output current i out data = 80 h 2ma capacitive load 2 c l no oscillation 50 pf logic inputs logic input low voltage v il 0.8 v logic input high voltage v ih 2.4 v logic input current i il 10 m a logic input capacitance 2 c il 10 pf logic outputs logic out high voltage v oh i oh = C0.4 ma 3.5 v logic out low voltage v ol i ol = 1.6 ma 0.4 v ac characteristics 2 reference in bandwidth bw C3 db frequency, v ref = 2.5 v dc + 0.1 v ac 500 khz slew rate sr for d v ref or fs code change 4 7 v/ m s voltage noise density e n f = 1 khz, v ref = 0 v 46 nv/ ? hz digital feedthrough ft digital inputs to dac outputs 10 nvs voltage output settling time 3 t s1 1 lsb of final value, fs data change 1 2 m s voltage output settling time 3 t s2 1 lsb of final value, d v ref = 1 v, data = ff h 12 m s power supplies positive supply current i cc v ih = 5 v, v il = 0 v, v ee = C5 v, no load 22 35 ma negative supply current i ee v ih = 5 v, v il = 0 v, v ee = C5 v, no load 22 35 ma logic supply currents i dd1&2 v ih = 5 v, v il = 0 v, v ee = C5 v, no load 0.1 ma power dissipation 4 p diss v ih = 5 v, v il = 0 v, v ee = C5 v, no load 225 350 mw power supply sensitivity pss d v cc & d v ee = 5% 0.007 %/% logic power supply range v ddr 4.75 5.25 v pos power supply range 2 v ccr v dd 7.0 v neg power supply range 2 v eer C5.25 0.0 v notes 1 when v ref = +3.500 v, 1 lsb = 13.67 mv. 2 guaranteed by design not subject to production test. 3 settling time test is performed using r l = 50 k w and c l = 35 pf. 4 power dissipation is calculated using 5 v (i dd + |i ss | + i dd1 + i dd2 ). specifications subject to change without notice. dual supply (@ v dd1 = v dd2 = v cc = +5 v 5%, v ee = C5 v 5%, v ref = +3.500 v, C40 c t a +85 c, unless otherwise noted) ad8600 rev. 0 C3C
rev. 0 C4C ad8600 electrical characteristics parameter symbol condition min typ max units interface timing 1, 2 clock ( en ) frequency f clk data loading 12.5 mhz clock ( en ) high pulse width t ch 40 ns clock ( en ) lowpulse width t cl 40 ns data setup time t ds 40 ns data hold time t dh 10 ns address setup time t as 0n s address hold time t ah 0n s valid address to data valid t ad 160 ns load enable setup time t ls 0n s load enable hold time t lh 0n s read/write to clock ( en )t rwc 30 ns read/write to databus hi-z t rwz 120 ns read/write to databus active t rwd 120 ns clock ( en ) to read/write t twh 0n s clock ( en ) to chip select t tch 0n s chip select to clock ( en )t csc 30 ns chip select to data valid t csd 120 ns chip select to databus hi-z t csz 150 ns reset pulse width t rs 25 ns notes 1 guaranteed by design not subject to production test. 2 all logic input signals have maximum rise and fall times of 2 ns. specifications subject to change without notice. figure 3. readback timing figure 2. write timing (@ v dd1 = v dd2 = v cc = +5 v 5%, v ee = C5 v, v ref = +3.500 v, C40 c t a +85 c, unless otherwise noted) t rwz t dh t twh high-z t as t ah t ch t cl t tch r/ w data addr en cs t csc t rwc t ds figure 4. write to dac register & voltage output settling timing (cs= high, prevents input register changes) t ls t lh t s1 t rs out t s1 en rs ld t rwd high -z t ad t csz t csd r/ w data addr en cs
ad8600 rev. 0 C5C pin description pin no. name description 1 nc no connection 2v ref reference input voltage common to all dacs. 3 dacgnd dac analog ground return. sets analog zero-scale voltage. 4v cc output amplifier positive supply 5v ee output amplifier negative supply 6 o7 dac channel output no. 7 7 o6 dac channel output no. 6 8 o5 dac channel output no. 5 9 o4 dac channel output no. 4 10 o3 dac channel output no. 3 11 o2 dac channel output no. 2 12 o1 dac channel output no. 1 13 o0 dac channel output no. 0 14 v dd1 digital logic power supply 15 rs active low reset input pin 16 db0 data bit zero i/o (lsb) 17 db1 data bit i/o 18 db2 data bit i/o 19 db3 data bit i/o 20 db4 data bit i/o 21 db5 data bit i/o 22 db6 data bit i/o 23 db7 most significant data bit i/o (msb) 24 a0 address bit zero (lsb) 25 a1 address bit 26 a2 address bit 27 a3 most significant addr bit (msb) 28 r/ w read/write select control input 29 en active low enable clock strobe 30 cs chip select input 31 ld dac register load strobe 32 dgnd1 digital ground input no. 1 33 o15 dac channel output no. 15 34 o14 dac channel output no. 14 35 o13 dac channel output no. 13 36 o12 dac channel output no. 12 37 o11 dac channel output no. 11 38 o10 dac channel output no. 10 39 o9 dac channel output no. 9 40 o8 dac channel output no. 8 41 v ee output amplifier negative supply 42 v cc output amplifier positive supply 43 dgnd2 digital ground input no. 2 44 v dd2 dac analog supply voltage warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8600 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings (t a = +25 c unless otherwise noted) v dd1 (digital supply) to gnd . . . . . . . . . . . . . . C0.3 v, +7 v v dd2 (dac buffer/driver supply) . . . . . . . . . . . . C0.3 v, +7 v v cc (analog supply) to gnd . . . . . . . . . . . . . . . C0.3 v, +7 v v ee (analog supply) to gnd . . . . . . . . . . . . . . . +0.3 v, C7 v v ref to gnd . . . . . . . . . . . . . . . . . . . . . . C0.3 v, v cc + 0.3 v v dd2 to v ref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v v out to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v cc short circuit duration v out to gnd or power supplies 1 . . . . . . . . . . . . . . . continuous digital input/output voltage to gnd . . . C0.3 v, v dd + 0.3 v thermal resistanceCtheta junction-to-ambient ( q ja ) plcc-44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 c/w package power dissipation . . . . . . . . . . . . . . . . (t j C t a )/ q ja maximum junction temperature t j max . . . . . . . . . . . 150 c operating temperature range . . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . +300 c note 1 no more than four outputs may be shorted to power or gnd simultaneously. pin configuration nc = no connect o9 o10 o13 o14 o15 o11 o12 o6 o5 o2 o1 o0 o4 o3 o7 v ee v ref nc v dd2 v cc db2 db3 db6 db7 a0 db4 db5 dacgnd v cc v ee o8 a2 a3 r/ w a1 dgnd2 ld cs en dgnd1 rs db0 db1 v dd1 4412 64 5 21 24 23 22 18 20 19 39 38 35 34 33 37 36 3 7 8 11 12 13 9 10 404142 25 28 27 26 43 31 30 29 32 15 16 17 14 top view (not to scale) ad8600 ordering guide package package model temperature description option ad8600ap C40 c to +85 c 44-lead plcc p-44a ad8600chips +25 c die* * for die specifications contact your local analog devices sales office. the ad8600 contains 5782 transistors.
rev. 0 C6C ad8600 transfer equations output voltage o i = d v ref 256 where i is the dac channel number and d is the decimal value of the dac register data. table i. truth table en r/ w cs ld rs operation write to dac register C x h l h update dac register l x h C h update dac register + x h l h latches dac register l x h + h latches dac register l l l l h dac register transparent write to input register l l l h h load data to input register at decoded address + l l h h latches data in input register at decoded address l l + h h latches data in input register at decoded address readback input registers x h l h h input register readback (data access) x h + h h hi-z readback disconnects from bus x x h x x hi-z on data bus reset x x x x l clear all registers to zero, v out = 0 v x x h h + latches all registers to zero lx lh + cs = low; input register ready for r /w, dac register latched to zero notes 1 + symbol means positive edge of control input line. 2 C symbol means negative edge of control input line. decoded dac register o i = a where a is the decimal value of the decoded address bits a3, a2, a1, a0 (lsb). address, cs , r/ w and data inputs should be stable prior to acti- vation of the active low en input. input registers are transpar- ent when en is low. when en returns high, data is latched into the decoded input register. when the load strobe ld and en pins are active low, all input register data is transferred to the dac registers. the dac registers are transparent while they are enabled. table ii. address decode table a3 a2 a1 a0 addr dac (msb) (lsb) code updated (binary) (hex) 0000 0 o0 0001 1 o1 0010 2 o2 0011 3 o3 0100 4 o4 0101 5 o5 0110 6 o6 0111 7 o7 1000 8 o8 1001 9 o9 1010 a o10 1011 b o11 1100 c o12 1101 d o13 1110 e o14 1111 f o15
typical performances characteristicsCad8600 rev. 0 C7C 0 ?/2 +1/2 ?/2 0 +1/2 256 0 192 128 64 digital input code ?decimal linearity error ?lsb dacs 00?7 superimposed dacs 08?15 superimposed v cc = +5v v ee = ?v v ref = +3.5v t a = +25 c figure 5. linearity error vs. digital code v out ?volts i out ?ma ?0 ?5 ? 5 0 15 10 ? ? ? 0 ? 1 2 3 4 v cc = +5v v ee = ?v rs = 0 figure 8. output current vs. voltage 0 0 1k 10k 10m 1m 100k ?0 ?5 ?5 ?0 ? frequency ?hz gain ?db phase ?degrees phase gain v in = 100mv p-p + 2.5v dc code = ff h t a = +25 c figure 11. gain & phase vs. frequency 3.47 3.48 3.49 3.50 125 ?5 ?0 100 75 50 25 0 temperature ? c full-scale output ?volts v cc = +5v v ee = ?v v ref = 3.5v figure 6. full-scale voltage vs. temperature 1 2 3 0 4 output amplitude ?volts time ?250ns/div v cc = +5v v ee = ?v v ref = 3.5v figure 9. full-scale settling time 100 1k 100k 10k frequency ?hz v in = 2v p-p + 1v dc rs = 0 t a = +25 c feedthrough ?db 0 ?0 ?0 ?0 ?0 ?00 figure 12. ac feedthrough vs. frequency 125 ?5?0 8 ? ? 0 4 100 7550250 temperature ? c zero-scale ?mv v cc = +5v v ee = ?v v ref = 3.5v figure 7. zero-scale voltage vs. temperature frequency ?hz 10 100 10k 1k 100 80 0 60 40 20 noise voltage density ?nv/ ? hz v cc = +5v v ee = ?v v ref = 0v t a = +25 c figure 10. voltage noise density vs. frequency 40 30 20 50 60 1k 10k 100 10 100k frequency ?hz psrr ?db d v cc = 100mv p-p t a = +25 c code = 00 h v ee = ?v figure 13. psrr vs. frequency
rev. 0 C8C ad8600 *patent pending. figure 14. supply current vs. temperature figure 15. output voltage drift accelerated by burn-in supply current ?ma temperature ? c 20 15 16 18 17 19 125 ?0 ?5 100 25 50 ?5 0 75 v cc = +5v v ee = ?v v ref = 3.5v c c + 3s c - 3s t = hours of operation at +125 c change in zero scale ?mv 1200 200 0 1000 600 800 400 c c + 3s c - 3s v cc = +5v v ee = ?v v ref = 3.5v code = 00 h ? ? 0 2 4 1 3 5 ? ? ? operation the ad8600 is a 16-channel voltage output, 8-bit digital to analog converter. the ad8600 operates from a single +5 v supply, or for a wider output swing range, the part can operate from dual supplies of 5 v or 6 v or a single supply of +7 v. the dacs are based upon a unique r-2r ladder structure* that removes the possibility of current injection from the refer- ence to ground during code switching. each of the 8-bit dacs has an output amplifier to provide 16 low impedance outputs. with a single external reference, 16 independent dc output lev- els can be programmed through a parallel digital interface. the interface includes 4 bits of address (a0Ca3), 8 bits of data (db0Cdb7), a read/write select pin (r/ w ), an enable clock strobe ( en ), a dac register load strobe ( ld ), and a chip select pin ( cs ). additionally a reset pin ( rs ) is provided to asynchro- nously reset all 16 dacs to 0 v output. d/a converter section the internal dac is an 8-bit voltage mode device with an out- put that swings from dacgnd to the external reference volt- age, v ref . the equivalent schematic of one of the dacs is shown in figure 16. the dac uses an r-2r ladder to ensure accuracy and linearity over the full temperature range of the part. the switches shown are actually n and p-channel mosfets to allow maximum flexibility and range in the choice of reference r r r v out r r r 2r r r r r r to 15 dacs v ref dacgnd *r = 30k w typically figure 16. equivalent schematic of analog channel voltage. the switches low on resistance and matching is im- portant in maintaining the accuracy of the r-2r ladder. amplifier section the output of the dac ladder is buffered by a rail-to-rail out- put amplifier. this amplifier is configured as a unity gain fol- lower as shown in figure 16. the input stage of the amplifier contains a pnp differential pair to provide low offset drift and noise. the output stage is shown in figure 17. it employs complementary bipolar transistors with their collectors con- nected to the output to provide rail-to-rail operation. the npn transistor enters into saturation as the output approaches the negative rail. thus, in single supply, the output low voltage is limited by the saturation voltage of the transistor. for the tran- sistors used in the ad8600, this is approximately 40 mv. the ad8600 was not designed to swing to the positive rail in con- trast to some of adis other dacs (for example, the ad8582). the output stage of the amplifier is actually capable of swinging to the positive rail, but the input stage limits this swing to ap- proximately 1.0 v below v cc . v ee v out v cc figure 17. equivalent analog output circuit during normal operation, the output stage can typically source and sink 1 ma of current. however, the actual short circuit current is much higher. in fact, each dac is capable of sourc- ing 20 ma and sinking 8 ma during a short condition. the absolute maximum ratings state that, at most, four dacs can be shorted simultaneously. this restriction is due to current densities in the metal traces. if the current density is too high, voltage drops in the traces will cause a loss in linearity perfor- mance for the other dacs in the package. thus to ensure long- term reliability, no more than four dacs should be shorted simultaneously.
ad8600 rev. 0 C9C power supply and grounding considerations the low power consumption of the ad8600 is a direct result of circuit design optimizing using a cbcmos process. the over- all power dissipation of 120 mw translates to a total supply cur- rent of only 24 ma for 16 dacs. thus, each dac consumes only 1.5 ma. because the digital interface is comprised entirely of cmos logic, the power dissipation is dependent upon the logic input levels. as expected for cmos, the lowest power dissipation is achieved when the input level is either close to ground or +5 v. thus, to minimize the power consumption, cmos logic should be used to interface to the ad8600. the ad8600 has multiple supply pins. v cc (pins 4 and 42) is the output amplifiers positive supply, and v ee (pins 5 and 41) the amplifiers negative supply. the digital input circuitry is powered by v dd1 (pin 14), and finally the dac register and r- 2r ladder switches are powered by v dd2 (pin 44). to minimize noise feedthrough from the supplies, each supply pin should be decoupled with a 0.1 m f ceramic capacitor close to the pin. when applying power to the device, it is important for the digi- tal supply, v dd2 , to power on before the reference voltage and for v ref to remain less than 0.3 v above v dd2 during normal operation. otherwise, an inherent diode will energize, and it could damage the ad8600. in order to improve esd resistance, the ad8600 has several esd protection diodes on its various pins. these diodes shunt esd energy to the power supplies and protect the sensitive ac- tive circuitry. during normal operation, all the esd diodes are reversed biased and do not affect the part. however, if overvolt- ages occur on the various inputs, these diodes will energize. if the overvoltage is due to esd, the electrical spike is typically short enough so that the part is not damaged. however, if the overvoltage is continuous and has sufficient current, the part could be damaged. to protect the part, it is important not to forward bias any of the esd protection diodes during normal operation or during power up. figure 18 shows the location of these diodes. for example, the digital inputs have diodes con- nected to v cc and from dgnd1. thus, the voltage on any digital input should never exceed the analog supply or drop be- low ground, which is also indicated in the absolute maximum ratings. dgnd1 v cc v dd2 dacgnd v ref all digital inputs (a0?3, db0?b7) (r/ w , cs , en, ld , rs ) figure 18. esd protection diode locations attention should be paid to the ground pins of the ad8600 to ensure that noise is not introduced to the output. the pin la- beled dacgnd (pin 3) is actually the ground for the r-2r ladder, and because of this, it is important to connect this pin to a high quality analog ground. ideally, the analog ground should be an actual ground plane. this helps create a low impedance, low noise ground to maintain accuracy in the analog circuitry. the digital ground pins (dgnd1 at pin 32 and dgnd2 at pin 43) provide the ground reference for the internal digital cir- cuitry and latches. the first thought may be to connect both of these pins to the system digital ground. however, this is not the best choice because of the high noise typically found on a systems digital ground. this noise can feed through to the out- put through the dacs ground pins. instead, dgnd1 and dgnd2 should be connected to the analog ground plane. the actual switching current in these pins is small and should not degrade the analog ground. 5 v output swing the output swing is limited to 1.0 v below the positive supply. this gives a maximum output of +4.0 v on a +5 v supply. to increase the output range, the analog supply, v cc , and the dac ladder supply, v dd2 , can be increased to +7 v. this allows an output of +5 v with a 5 v reference. v dd1 should remain at +5 v to ensure that the input logic levels do not change. reference input considerations the ad8600 is designed for one reference to drive all 16 dacs. the reference pin (v ref ) is connected directly to the r-2r lad- ders of each dac. with 16 dacs in parallel, the input imped- ance is typically 2 k w and a minimum of 1.2 k w . the input resistance is code dependent. thus, the chosen reference device must be able to drive this load. some examples of +2.5 v refer- ences that easily interface to the ad8600 are the ref43, ad680, and ad780. the unique architecture ensures that the reference does not have to supply shoot through current, which is a condition in some voltage mode dacs where the ref- erence is momentarily connected to ground through the cmos switches. by eliminating this possibility, all 16 dacs in the ad8600 can easily be driven from a single reference.
rev. 0 C10C ad8600 interface timing and control the ad8600 employs a double buffered dac structure with each dac channel having a unique input register and dac reg- ister as shown in the diagram entitled equivalent dac chan- nel on the first page of the data sheet. this structure allows maximum flexibility in loading the dacs. for example, each dac can be updated independently, or, if desired, all 16 input registers can be loaded, followed by a single ld strobe to up- date all 16 dacs simultaneously. an additional feature is the ability to read back from the input register to verify the dacs data. a0 a1 a2 a3 r/ w en cs r/ w cs ld en n4 n3 n2 n1 n6 n5 read back input register d7?0 r-2r ladder dac register 8 8 8 figure 19. logic interface circuit for dac channel 0 the interface logic for a single dac channel is shown in figure 19. this figure specifically shows the logic for channel 0; how- ever, by changing the address input configuration to gate n1, the other 15 channels are achieved. all of the logic for the ad8600 is level sensitive and not edge triggered. for example, if all the control inputs ( cs , r/ w , en , ld ) are low, the input and dac registers are transparent and any change in the digital inputs will immediately change the dacs r-2r ladder. table i details the different logic combinations and their effects. chip select ( cs ), enable ( en ) and r/ w must be low to write the input register. during this time that all three are low, any data on db7Cdb0 changes the contents of the input register. this data is not latched until either en or cs returns high. the data setup and hold times shown in the timing diagrams must be observed to ensure that the proper data is latched into the input register. to load multiple input registers in the fastest time possible, both r/ w and cs should remain low, and the en line be used to clock in the data. as the write timing diagram shows, the address should be updated at the same time as en goes low. before en returns high, valid data must be present for a time equal to the data setup time (t ds ), and after en returns high, the data hold time (t dh ) must be maintained. if these mini- mum times are violated, invalid data may be latched into the in- put register. this cycle can be repeated 16 times to load all of the dacs. the fastest interface time is equal to the sum of the low and high times (t cl and t ch ) for the en input, which gives a minimum of 80 ns. because the en input is used to clock in the data, it is often referred to as the clock input, and the timing specifications give a maximum clock frequency of 12.5 mhz, which is just the reciprocal of 80 ns. after all the input registers have been loaded, a single load strobe will transfer the contents of the input registers to the dac registers. en must also be low during this time. if the address or data on the inputs could change, then cs should be high during this time to ensure that new data is not loaded into an input register. alternatively, a single dac can be updated by first loading its input register and then transferring that to the dac register without loading the other 15 input registers. the final interface option is to read data from the dacs input registers, which is accomplished by setting r/ w high and bring- ing cs low. read back allows the microprocessor to verify that correct data has been loaded into the dacs. during this time en and ld should be high. after a delay equal to t rwd , the data bus becomes active and the contents of the input register are read back to the data pins, db0Cdb7. the address can be changed to look at the contents of all the input registers. note that after an address change, the valid data is not available for a time equal to t ad . the delay time is due to the internal readback buffers needing to charge up the data bus (measured with a 35 pf load). these buffers are low power and do not have high current to charge the bus quickly. when cs returns high, the data pins assume a high impedance state and control of the data lines or bus passes back to the microprocessor.
ad8600 rev. 0 C11C unipolar output operation the ad8600 is configured to give unipolar operation. the full- scale output voltage is equivalent to the reference input voltage minus 1 lsb. the output is dependent upon the digital code and follows table iii. the actual numbers given for the analog output are calculated assuming a +2.5 v reference. table iii. unipolar code table dac binary input msb lsb analog output 1 1 1 1 1 1 1 1 +v ref (255/256) = +2.49 v 1 0 0 0 0 0 0 1 +v ref (129/256) = +1.26 v 1 0 0 0 0 0 0 0 +v ref (128/256) = +1.25 v 0 1 1 1 1 1 1 1 +v ref (127/256) = +1.24 v 0 0 0 0 0 0 0 1 +v ref (001/256) = +0.01 v 0 0 0 0 0 0 0 0 +v ref (000/256) = +0.00 v bipolar output operation the ad8600 can be configured for bipolar operation with the addition of an op amp for each output as shown in figure 20. the output will now have a swing of v ref , as detailed in table iv. this modification is only needed on those channels that re- quire bipolar outputs. for channels which only require unipolar output, no external amplifier is needed. the op495 quad am- plifier is chosen for the external amplifier because of its low power, rail-to-rail output swing, and dc accuracy. again, the values calculated for the analog output are based upon an as- sumed +2.5 v reference. out 1/4 op495 +5v ?v r1 10k v out r1 10k v ref v ref ad8600 figure 20. circuit for bipolar output operation table iv. bipolar code table dac binary input msb lsb analog output 1 1 1 1 1 1 1 1 +2 v ref (255/256) C v ref = +2.49 v 1 0 0 0 0 0 0 1 +2 v ref (129/256) C v ref = +0.02 v 1 0 0 0 0 0 0 0 +2 v ref (128/256) C v ref = +0.00 v 0 1 1 1 1 1 1 1 +2 v ref (127/256) C v ref = C0.02 v 0 0 0 0 0 0 0 1 +2 v ref (001/256) C v ref = C2.48 v 0 0 0 0 0 0 0 0 +2 v ref (000/256) C v ref = C2.50 v interfacing to the 68hc11 microcontroller the 68hc11 is a popular microcontroller from motorola, which is easily interfaced to the ad8600. the connections be- tween the two components are shown in figure 21. port c of the 68hc11 is used as a bidirectional input/output data port to write to and read from the ad8600. port b is used for address- ing and control information. the bottom 4 lsbs of port b are the address, and the top 4 msbs are the control lines ( ld , cs , en , and r/ w ). the microcode for the 68 hc11 is shown in figure 22. the comments in the program explain the function of each step. three routines are included in this listing: read from the ad8600, write to the ad8600, and a continuous loop that generates a saw-tooth waveform. this loop is used in the application below. db0?b7 a0?3 ld en r/ w cs dgnd1, dgnd2 dacgnd 8 4 digital ground analog ground ad8600 motorola 68hc11 pc0?c7 pb0?b3 pb4 pb5 pb6 pb7 gnd figure 21. interfacing the 68hc11 to the ad8600
rev. 0 C12C ad8600 * this program contains subroutines to read and write * to the ad8600 from the 68hc11. additionally, a ramp * program has been included, to continuously ramp the * output giving a triangle wave output. * * the following connections need to be made: * 68hc11 ad8600 * gnd dgnd1,2 * pc0-pc7 db0Cdb7 respectively, data port * pb0-pb3 a0Ca3 respectively, address port * pb4 ld * pb5 en * pb6 r/w * pb7 cs * portc equ $1003 define port addresses portb equ $1004 ddrc equ $1007 * org $c000 read lds #$cfff subroutine to read from ad8600 * ldaa #$00 initialize port c to 00000000 staa ddrc configures pc0-pc7 as inputs. * ldx #$00 points to dac address in 68hc11 memory ldaa 0,x put the address in the accumulator adda #$70 add the control bits to the address * r/w, ld, en are high, cs is low. staa portb output control and address on port b. * inx points to memory location to store the data ldaa portc read data from dac staa 0,x store this data in memory at address x * ldy #$1000 bset portb,y $f0 set cs, ld, en high jmp $e000 return to buffalo * * write lds #$cfff routine to write to ad8600 ldaa #$ff initialize port c to 11111111 staa ddrc configures pc0-pc7 as outputs. * ldx #$00 points to dac address in 68hc11 mem ldaa 0,x puts the address in the accumulator adda #$30 set cs, r/w low and ld, en high staa portb output to portb for control and address * inx points to memory location to store the data ldaa 0,x load the data into the accumulator staa portc write the data to the dac * ldy #$1000 bclr portb,y $30 set ld, en low to latch data bset portb,y $b0 bring ld, en, cs high, write is complete * jmp $e000 return to buffalo * * ramp lds #$cfff routine to generate a triangle wave ldaa #$ff configure port c as outputs
ad8600 rev. 0 C13C staa ddrc * ldx #$00 set x to point to the dac address ldaa 0,x load the address from 68hc11 mem staa portb set the address on portb * ld, cs, en, r/w are all low for * transparent dac loading ldab #$ff set accumulator b to 255 * loop ldaa #$00 start the triangle wave at zero staa portc write the data to the ad8600 * load inca increase the data by one staa portc send the new data to the ad8600 cba compare a to b bne load we havent reached 255 yet jmp loop we have reached 255, so start over figure 22. 68hc11 microcode to interface to the ad8600. time dependent variable gain amplifier using the ad600 the ad8600 is ideal for generating a control signal to set the gain of the ad600, a wideband, low noise variable gain ampli- fier. the ad600 (and similar parts such as the ad602 and ad603) is often used in ultrasound applications, which require the gain to vary with time. when a burst of ultrasound is ap- plied, the reflections from near objects are much stronger than from far objects. to accurately resolve the far objects, the gain must be greater than for the near objects. additionally, the sig- nals take longer to reach the ultrasound sensor when reflected from a distant object. thus, the gain must increase as the time increases. the ad600 requires a dc voltage to adjust its gain over a 40 db range. since it is a dual, the two variable gain amplifiers can be cascaded to achieve 80 db of gain. the ad8600 is used to generate a ramped output to control the gain of the ad600. the slope of the ramp should correspond to the time delay of the ultrasound signal. since ultrasound applications often require multiple channels, the ad8600 is ideal for this application. the circuit to achieve a time dependent variable gain amp is shown in figure 23. the ad600s gain is controlled by differ- ential inputs, c1lo and c1hi, with a gain constant of 32 db/v. thus for 40 db of gain, the differential control input needs to be 1.25 v. in this application, the c1lo input is set at the midscale voltage of 0.625 v, which is generated by a simple voltage divider from the ref43. the ad8600s output is di- vided in half, generating a 0 v to 1.25 v ramp, and then applied to c1hi. this ramp sweeps the gain from 0 db to 40 db. o +5 v ?v v out r1 10k v in v ref v cc , v dd1 , v dd2 ad8600 2 13 r2 10k +5 v c1 100pf 0v 1.25v 46 ref43 +5 v 2 +2.5v digital control c1hi 16 2 3 a1hi a1lo 4 gat1 1 c1lo v pos 13 12 15 a1cm 14 a1op ad600 r3 30k r4 10k (from ultrasound sensor) 0.625v figure 23. ultrasound amplifier with digitally controlled variable gain
rev. 0 C14C ad8600 the functionality of this circuit is shown in the scope photo in figure 24 the top trace is the control ramp, which goes from 0 v to 1.25 v. the bottom trace is the output of the ad600. the input is actually a 12 mv p-p, 10 khz sine wave. thus, the bottom trace shows the envelop of this waveform to illustrate the increase in gain as time progresses. this ramp was gener- ated under control of the 68hc11 using the ramp subroutine as mentioned above. the slope of the ramp can easily be lengthened by adding some delay in the loop, or the slope can be increased by stepping by 2 or more lsbs instead of the cur- rent 1 lsb changes. gain control 1v/div ad600 output 0.2v/div 200?/div figure 24. time dependent gain of the ad600 glitch impulse a specification of interest in many dac applications is the glitch impulse. this is the amount of energy contained in any overshoot when a dac changes at its major carry transition, in other words, when the dac switches from code 01111111 to code 10000000. this point is the most demanding because all of the r-2r ladder switches are changing state. the ad8600s glitch impulse is shown in figure 25. calculating the value of the glitch is accomplished by calculating the area of the pulse, which for the ad8600 is: glitch impulse = (1/2) (100 mv) (200 ns) = 10 nv sec. 200ns/div200ns/div v out 50mv/div figure 25. glitch impulse
ad8600 rev. 0 C15C outline dimensions dimensions shown in inches and (mm). 44-lead plastic lead chip carrier (plcc) package (p-44a) 0.032 (0.81) 0.026 (0.66) 0.021 (0.53) 0.013 (0.33) 0.056 (1.42) 0.042 (1.07) 0.025 (0.63) 0.015 (0.38) 0.180 (4.57) 0.165 (4.19) 0.63 (16.00) 0.59 (14.99) 0.110 (2.79) 0.085 (2.16) 0.040 (1.01) 0.025 (0.64) 0.050 (1.27) bsc 0.656 (16.66) 0.650 (16.51) sq 0.695 (17.65) 0.685 (17.40) sq 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 40 6 top view 39 29 18 17 pin 1 identifier 7 28 0.020 (0.50) r
rev. 0 C16C ad8600 printed in u.s.a. c1921C18C7/94

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